FlowCAD EDA Software für PCB, FPGA, Package und ASIC Design FlowCAD

Skalierbare Cadence PCB Editor Lösung


Die Cadence PCB Layout Produkte sind innerhalb der OrCAD-Produktlinie und auch innerhalb Allegro-Produktfamilie skalierbar. In dieser Tabelle sind die 3 Versionen des OrCAD PCB Editors und der Allegro PCB Designer miteinander verglichen. Zum Allegro PCB Designer gibt es noch mehrere Optionen, die den Funktionsumfang zusätzlich erweitern.
Dieser Vergleich basiert auf der Version 17.2 für OrCAD und Allegro. Für mehr Informationen wenden Sie sich bitte an unsere Mitarbeiter.

  OrCAD Lite OrCAD PCB Designer Standard OrCAD PCB Designer Professional Allegro PCB Designer
PCB Editor Place and Route
Unlimited Database limited
Cross place and cross probe with OrCAD Capture limited
Pad stack and footprint editor limited
STEP, 3D visualization, and flip board limited
Customizable drill legend and NC output limited
Via-in-pad rules, blind/buried via support limited
Auto placement, quick place, and floor planning limited
Dynamic shapes with real-time plowing and healing limited
2D drafting and associative dimensioning limited
Gerber 274x, 274D artwork output generation limited
IPC-2581 import and export limited
HTML-based reports limited
DFM DRCs limited
Interactive etch editing (push and shove of traces) limited
Automatic silkscreen generation limited
Intelligent split-plane support limited
SKILL runtime, macro, and scripting support limited
Variant assembly and BOM creation limited
PCB/CAD interfaces - IFF, Layout, PADS®, P-CAD® limited
PCB Design Import Eagle®, Altium® -
Mechanical CAD interfaces - DXF, IDX, IDF limited
Manual test prep (test point generation and use) limited
Snap functions (precise drafting of lines and shapes) limited
SameNet clearance DRC support limited
Stacked via edit, move limited
Single-sided design jumper support limited
Scribble Routing limited
Differential pair routing and rules support limited  
Placement and circuit replication  limited  
Component alignment functions limited  
Blind / Buried Micro via stacking, split, and merge limited  
Interactive delay tuning limited  
Automatic test prep (generation and reuse) limited  
Constraint region constraints limited  
Min/max-length rules support limited  
Min/max-propagation rules support limited  
Relative propagation rules support limited  
Constraint feedback heads-up displays limited  
Via arrays limited  
Interconnect Floor Planner (IFP)  
Design for Assembly Rules (DFA)  
Allegro Team Design Option   Option
Allegro High-Speed Option   Option
Allegro Miniaturization Option   Option
Allegro Analog/RF Option   Option
Allegro Design Planning Option   Option
Allegro Manufacturing Option   Option
Rigid Flex Technologies
Cross Section support for mask/coating layers limited
Native database flex and surface finish layers limited
Auto-rounding shape corners limited
Dynamic cross hatch and solid planes limited
Cross section by zone limited
Inter layer DRC (mask/mask; mask/surface conductor) limited
Zone table chart for manufacturing limited
Dynamic zone placement (auto drop down) limited
Techfile support of zones limited
Curved fillets limited
6-signal-layer autorouting limited  
256-signal-layer autorouting limited   Autointeractive Option
Shape-based or gridded autorouting limited   
SMD fanout limited   
Trace width by net and net class limited   
45-degree and memory pattern routing limited    
Interactive routing with shoving and plowing limited   
Interactive floor planning limited    
Online design rule checking limited   
Flip, rotate, align, push, and move components limited   
Placement density analysis limited   
Allegro PCB Routing Option   Option
Constraint Manager
Physical rules limited
Spacing rules limited
SameNet rules limited
Properties and DRCs limited
Differential pairs and static phase control limited    
Region rules limited    
Single line impedance rules limited    
Min. / Max. propagation rules limited    
Relative propagation rules limited   
Schematic Entry and Circuit Design
Graphical, flat, and hierarchical design limited
Heterogeneous bus and NetGroup support limited
Unlimited undo/redo limited
Dynamically update hierarchical blocks limited
Design reuse limited
Reference external designs and circuits limited
Tcl-scripting language for customization limited
Online design rule check limited
Unlimited user-defined properties limited
Heterogeneous and homogeneous parts support limited
PCB forward- and back-annotation limited
Schematic part and library editor limited
PCB cross probing and cross-placement limited
FPGA design-in support limited
FPGA bi-directional support limited
Intelligent PDF creation limited
Import PADS® schematic design limited
Import Altium® schematic design -
Import Eagle® schematic design -
Component Information System
Centralized part information system limited CIS option CIS option
ODBC-compliant database support limited CIS option CIS option
Relational data support limited CIS option CIS option
MRP, ERP, and PLM integration limited CIS option CIS option
Graphical preview of database parts limited CIS option CIS option
Intelligent database query limited CIS option CIS option
Component property validation limited CIS option CIS option
Temporary new part introduction limited CIS option CIS option
Extensive reports and report templates limited CIS option CIS option
Crystal Reports for advanced documentation limited CIS option CIS option
Assembly Variants
Unlimited assembly variant support limited CIS option CIS option
Part substitution and part "not present" support limited CIS option CIS option
Variant comparison reports limited CIS option CIS option
Print capabilities for variants limited CIS option CIS option
Signal Integrity
Pre- and post-route signal integrity analysis limited
Graphical topology definition and exploration limited
Interactive waveform viewer limited
OrCAD Capture SI integration and flow limited
Macro modelling support (DML) limited
IBIS 5.0 and ICM model support limited
Spectre®-to-DML and HSpice-to-IBIS conversion limited
Lossy transmission lines limited
Coupled (3 net) simulation  limited
Differential-pair exploration and simulation limited
Single net extraction from PCB Editor limited
Post- route signal integrity analysis limited
Xtalk Table
Model Dump
Design Link
Diese Tabelle ist ohne Gewähr. Verbindliche Informationen entnehmen Sie bitte den offiziellen Datenblättern von Cadence.